The invention relates generally to computer systems. In particular, the invention relates to the sharing of an interrupt level by multiple interrupt sources.
Many computer systems rely upon the use of interrupts to allow, for instance, peripheral devices to request servicing by the central processor. The peripheral device issues an interrupt request to an interrupt handler associated with the processor. When the interrupt handler receives the interrupt request, the normal execution of the processor is interrupted and the processor goes into an interrupt handling procedure. A popular type of interrupt handler is the 8259, manufactured by the Intel Corporation. The 8259 provides for eight different levels of prioritized interrupts so that eight different interrupting peripheral devices can be supported. However, as computer systems have become more complex, more than eight peripheral devices need to be provided for. Bradley et al. in U.S. patent application No. 629,868, filed July 11, 1984, now U.S. Pat. No. 4,631,670, and incorporated herein by reference, describe a method of interrupt level sharing such that more than one peripheral device can use a single interrupt level. One simple embodiment of Bradley's invention is shown in FIG. 1 for an interrupt circuit 10. An interrupt request line 12 is connected in parallel to this and other interrupt circuits 10. The shared interrupt request line 12 is also connected to the 8259 interrupt handler. Assuming that there are no outstanding interrupt requests for the interrupt level associated with the interrupt request line 12, the peripheral device associated with the illustrated interrupt circuit 10 requests an interrupt service by issuing a continued high signal INTERRUPT. An AND gate 14 receives this signal INTERRUPT and, in the absence of other outstanding requests, passes the interrupt request to a one shot pulse generator 16. Again, the pulse generator 16 is enabled in the absence of an outstanding service request and for a pulse duration it enables an output amplifier 18. The output amplifier 18 has its input connected to ground and its output separated from a positive voltage by a resistor 20. Therefore, during the pulse width of the pulse generator 16, the interrupt request line 12 is brought to ground. Otherwise, the illustrated interrupt circuit 10 presents a high impedance to the interrupt request line 12. Because of this high impedance, other interrupt circuits attached to the same interrupt request line 12 can likewise produce a negative pulse on the interrupt request line 12.
The 8259 interrupt handler does not respond to the negative transition of the negative pulse but rather to the final positive transition of the negative pulse on the interrupt request line 12. This same upward transition clocks the flip-flop 22 to produce a low complemented output -Q3 that disables the pulse generator 16. As a result, the pulse generator 16 remains disabled until a software generated REENABLE signal clears the flip-flop 22. The preceding discussion of the disabling and reenabling applies whether the negative pulse on the interrupt request line 12 originated in the illustrated interrupt circuits or one of the other interrupt circuits. The effect of the interrupt circuit 10 is to lock out any further interrupt requests until the software generated REENABLE signal indicates that the interrupt service has been completed.
It should be noted that the interrupt handling routine that the processor performs upon receipt of an interrupt request usually polls all the peripheral devices attached to that interrupt request line 12 to determine which device is requesting the interrupt. This polling is done by separate signal lines, not shown. Once a peripheral device has been serviced for its interrupt request, it removes its internal interrupt request INTERRUPT. If the polling does not uncover all interrupt requests, such as when the processor polls only once and the peripheral device requests its interrupt just after being polled, the internal interrupt signal INTERRUPT remains high and the removal of the disabling causes another negative pulse to be impressed on the interrupt request line 12.
The inventor has discovered a problem with the interrupt circuit of Bradley et al. The 8259 requires that the negative pulse on the interrupt request line have a minimum duration of 125 nanoseconds. For any shorter pulse, the 8259 does not recognize the interrupt request and accordingly the interrupt handling procedures are not initiated. However, the inhibiting flip-flop 22 of Bradley et al. responds much more quickly so that a negative pulse of, for example, 5 nanoseconds, will cause the flip-flop 22 to lock out this interrupt circuit 10 and all similar interrupt circuits. Assuming that all the peripheral devices have similar interrupt circuits, any such accidental lock out means that there will be no more interrupt requests. Accordingly, the processor has no reason to enter its interrupt handling procedure and thus to eventually reenable the interrupt circuits. Bradley also discusses a clocked embodiment of an interrupt circuit. This embodiment is slightly more complex than the non-clocked embodiment of FIG. 1, but, nonetheless, it is simple enough that it also is inhibited by a negative pulse considerably less than 125 nanoseconds.
The inventor has further determined that the interrupt request line 12 is relatively noisy and contains frequent noise pulses having a duration of less than 20 nanoseconds. The interrupt request line 12 is often left in a high impedance state so that it is then acting as an antenna for spurious signals. It would be possible to reduce the noise on the interrupt request line 12 by the use of coaxial cable. However, the interrupt request line is very often wired between corresponding pins of several edge connectors. The use of coaxial cable for such a connection is considered to be unduly expensive.
Another possible solution would be to attach a low-pass filter to the interrupt request line 12 or possible to include this low-pass filter in the feedback to the flip-flop 22. However, such a filter would smooth the transitions of all signals on the interrupt request line 12, thus slowing the response and running counter to the standard practice of maintaining the transitions as sharp as possible.